main.CPUClock=3500KHz
main.Caption="Àðãî"
main.ff.speed=10
main.ff.keymask[B]=2

CPU : Z80 {
  debug=cas
  mem=mm
  pc=F800
  port[00-FF]=portmap
  rst[0]=kbd.irq
  -rst[7]=crt.irq
}

portmap : MemMap2 {
  map[80]=sysctl
  map[81]=casctl
  map[A1].ro=kbd.~idata
  map[A1].wo=dmmr0
  map[A0]=tim.data
  map[A2]=tim.data
  map[A4]=tim.data
  map[A6]=tim.data
  map[A2].offset=1
  map[A4].offset=2
  map[A6].offset=3
  map[A9].wo=dmmr1
  map[B9]=mmr1
  map[C0]=crt.data
  map[C4]=crt.data
  map[C4].offset=1
  map[C1]=com.data
  map[C3]=com.data
  map[C3].offset=1
  map[E0-EF]=dma.data
  map[FE].wo=sysctl
}

mem1 : Memory {
  size=20000
}

bios : Memory {
  rom="Argo\argo.bin"
}

sysctl : Register {
  write[4]=beep.input
}

fontdc : Decoder {
  mem=mem1[1F800]
  adrxlat="CB98765A43210"
}

crt : K580wg75 {
  mode=0
  dma=dma[2]
  font=fontdc
  fontwidth=8
  fontmode=128
  palette="Unior\palette.rom"
  pindex=crt.ggh
}

dmm0 : MemMap {
  map[0][0000-FFFF]=mem1[00000]
  map[1][0000-FFFF]=mem1[10000]
  map[2][0000-FFFF]=dummy
  map[3][0000-FFFF]=dummy
  map[4][0000-FFFF]=dummy
  map[5][0000-FFFF]=dummy
  map[6][0000-FFFF]=dummy
  map[7][0000-FFFF]=dummy
}

dmm1 : MemMap {
  map[0][0000-FFFF]=mem1[00000]
  map[1][0000-FFFF]=mem1[10000]
  map[2][0000-FFFF]=dummy
  map[3][0000-FFFF]=dummy
  map[4][0000-FFFF]=dummy
  map[5][0000-FFFF]=dummy
  map[6][0000-FFFF]=dummy
  map[7][0000-FFFF]=dummy
}

dmmr0 : Register {
  write[1-3]=dmm0.page
}

dmmr1 : Register {
  write[1-3]=dmm1.page
}

dma : K580wt57 {
  mem[0]=dmm0
  mem[1]=dmm1
  mem[2]=mem1
  autocopy=1
  hrq=CPU.hold
  tc=crt.stopdrq
}

tim : K580wi53 {
  clock[0].rate=3/4
  clock[1].rate=1/1
  clock[2].rate=1/8e
  gate[0].value=1
  gate[1].value=1
  gate[2].value=1
}

com : K580ww51 {
  io=cas.ioctl
}

mmr1 : Register {
  write[1]=mm.page
}

mm : MemMap {
  map[0][0000-F7FF]=mem1[0000]
  map[0][F800-FFFF].wo=mem1[F800]
  map[0][F800-FFFF].ro=bios[0000]
  map[1][0000-F7FF]=mem1[0000]
  map[1][F800-FFFF].wo=mem1[1F800]
  map[1][F800-FFFF].ro=bios[0000]
}

kbd : Keyboard {
  mask=CPU.port.msb
  layout="Argo\layout.kbd"
  irqkey=58
}

beep : beep {
}

casctl : Register {
 write[1]=cas.ioctl.rec
 write[2]=cas.ioctl.play
 write[3]=cas.ioctl.back
 write[4]=cas.ioctl.ff
 write[5]=cas.ioctl.stop
}

cas : tape-recorder {
}
